1. Field of the Invention
The present invention relates to an improvement of a successive approximation analog to digital (hereinafter referred to as A/D) converter, and, more particularly, to an A/D converter having an offset compensation circuit for automatically compensating for an offset error of an A/D converter.
2. Description of the Related Art
FIG. 1 illustrates an example of the structure of a successive approximation A/D converter of a voltage comparison type. Such an A/D converter is disclosed in, for example, "Digest of Technical Papers", p154, of 1976, IEEE International Solid-state Circuits Conference.
The converting operation of the A/D converter shown in FIG. 1 will be described with reference to FIG. 2. For ease of understanding, it is assumed that the input data and analog output voltage V.sub.D of a D/A converter 51 has the relation as indicated in the case of "No Offset Output" in FIG. 2 and that the analog input voltage V.sub.A is 2.3 V.
A controller 50 connects a switch S.sub.1 to the analog input voltage V.sub.A and turns a switch S.sub.2 ON. A charging voltage V.sub.A of a capacitor C.sub.SH is V.sub.A = 2.3 V + V.sub.COF, where V.sub.COF is an offset voltage of a comparator CP and is ideally 0 V. Controller 50 sets only the most significant bit (MSB) of a 5-bit successive approximation register SAR to "1". The output of this register SAR is "10000". It is clear from FIG. 2 that the output voltage V.sub.D of D/A converter 51 is 1.6 V. Controller 50 then turns switch S.sub.2 off and connects switch S.sub.1 to the output V.sub.D of D/A converter 51.
Comparator CP compares the voltage V.sub.A held in capacitor C.sub.SH with the output voltage V.sub.D of D/A converter 51. In this case, V.sub.A (= 2.3 V) &gt; V.sub.D (= 1.6 V). While keeping the MSB of register SAR at "1" (MSB of register SAR is reset to "0" when V.sub.A &lt; V.sub.D), controller 50 sets the second bit, one bit lower than the MSB, to "1". The output of register SAR becomes "11000" and the output of D/A converter 51, V.sub.D becomes 2.4 V.
Comparator CP compares the voltage V.sub.A with the voltage V.sub.D and indicates V.sub.A &lt; V.sub.D. In response to the comparison result, controller 50 resets the second bit of register SAR to "0" and sets the third bit to "1". As a result, the output of register SAR becomes "10100"
with the voltage V.sub.D being 2.0 V. Accordingly, the comparison result from comparator CP is V.sub.A &gt;V.sub.D. Controller 50 then set the fourth bit of register SAR at "1" while keeping the third bit of register SAR at "1".
The output of register SAR becomes "10110" and the output voltage V.sub.D become 2.2 V, which means V.sub.A &gt;V.sub.D. Controller 50 then sets the least significant bit (LSB) of register SAR to "1" while keeping the fourth bit of register SAR at "1". The output of register SAR becomes "10111" and the output voltage V.sub.D becomes 2.3 V, which means V.sub.A = V.sub.D.
To minimize the quantitative error in practical A/D converter, D/A converter 51 is given an offset corresponding to -1/2 LSB (0.05 V in this case). When the input analog voltage V.sub.A is 2.25 &lt; V.sub.A &lt; 2.35 V, the A/D conversion output is therefore "10111".
In sampling the analog input voltage V.sub.A in the A/D converter shown in FIG. 1, the sum of this voltage V.sub.A and the offset voltage V.sub.COF of comparator CP is charged in capacitor C.sub.SH, and this charged voltage (V.sub.A + V.sub.COF ) becomes a reference voltage for the comparing operation of comparator CP. Thus, the comparison result from comparator CP is expressed as .vertline.G.sub.C .vertline. .times.{(V.sub.D + V.sub.COF ) -(V.sub.A + V.sub.COF)} where .vertline.G.sub.C .vertline. is the absolute value of the gain of the comparator. In the case where a comparator CP having a sample/hold function is used, then even if an offset voltage exists in comparator CP, the comparison result is free from the influence of such an offset voltage.
It often occurs that the analog input voltage V.sub.A input into an A/D converter does not have a sufficiently large amplitude. In such a case, this results in the resolution of the A/D converter being under-utilized. To cater for this situation, therefore, an amplifier 52 for amplifying the analog input voltage is often provided, as indicated by the broken line in FIG. 1.
However, an offset voltage V.sub.AOF is generated between the input and output terminals of amplifier 52, therefore comparator CP will have an output of .vertline.G.sub.C .vertline..times.[(V.sub.D + V.sub.COF ) -{.vertline.G.sub.A .vertline..times. (V.sub.A + V.sub.AOF) + V.sub.COF }]. As indicated by this equation, when the offset voltage V.sub.AOF exists, the offset voltage of amplifier 52 affects the output of comparator CP, so that the result of a comparison of the output voltage V.sub.D of D/A converter 51 with the analog input voltage V.sub.A would not reflect the true value, resulting in generation of a large offset error.
Another example of an A/D converter is a type which uses a comparator having no sample/hold function and an exclusive sample/hold circuit which performs the sample/hold operation on the analog input voltage V.sub.A and supplies the resultant voltage to the comparator. With this structure, an offset, if present between the input and output of comparator CP, would, unlike in the case of the structure shown in FIG. 1, generate an offset error.